1. Field of the Invention
The present invention relates to an arithmetic circuit, and more particularly to an arithmetic circuit using a bit arithmetic unit to perform an integer division on digital image signals.
2. Related Art
In the conventional signal processing, as for integer division, multipliers are mostly adopted to obtain an approximate result:
                    R        =                  N          14                                    Equation        ⁢                                  ⁢        1            
Then, “14” in Equation 1 is converted into a power of 2 (for example, “1024”), and then Equation 1 is modified into Equation 2:
                    R        =                              N            14                    ≈                                    73              ×              N                        1024                                              Equation        ⁢                                  ⁢        2            
According to Equation 2, General Equation 3 is obtained:
                              R          =                                    N              D                        ≈                                          C                ×                N                            S                                      ⁢                                  ⁢                              C            =                          S              D                                ,                                    Equation        ⁢                                  ⁢        3            and the S is a power of 2. When the denominator is a power of 2, a right shift operation is used to replace the division operation in the prior art. Therefore, a divider can be achieved simply by one multiplier and a bit operation once, which is based upon the precondition that the divisor D should be a fixed value and needs to be simplified in advance when designing the circuit. However, in practice, the divisor D varies as the signal processing proceeds. Therefore, if it intends to replace the divider as above described, the multiplier factor C needs to be pre-stored in a memory of a computer device. The wider the variation range of the divisor D is, the more variables C needs to be stored, and thus, the memory space needs to be enlarged accordingly.